cd40718, cd40728, cd40758 typ s cos/mos or gates high-voltage types (20-volt rating) cd40718 quad 2-lnput or gate cd40728 dual 4-lnput or gate cd40758 triple 3-lnput or gate the rca-c04071 b, c04072b, and cd4075b or gates provide the system designer with direct implementation of the positive-logic or function and supplement the existing family of cos/mas gates. the cd4071, cd4072, and c04075 types are supplied in 14-lead dual-in-line ceramic packages (0 and f suffixes), 14-lead dual- in-line plastic packages (e suffix), 14-lead ceramic flat packages (k suffix), and in chip form (h suffix). features: ? nledium-speed operation-tplh' tphl = 60 ns (typ.) at vdd = 10 v ? 100% tested for quiescent current at 20 v ? maximum input current of 1 j.1.a at 18 v over full package-temperature range; 100 na at 18 v and 25 0 c ? standardized, symmetrical output characteristics ? noise margin (over full package temperature range) 1 vat vdd = 5 v 2 v at vdd = 10 v 2.5 vat vdd = 15 v ? 5v, 10-v, and 16-v parametric ratings ? meets all requirements of jedec tenta tive stilndard ~o. 13 a, "standard specifications for description of 'b' series cmos devices" recommended operating conditions for maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: characteristic limits units min. i max. supply voltage range (for t a = full packagetemperature range) 3 i 18 v static electrical characteristics limits at indicated temperatures (oci conditions valuesat-55,+25,+125 apply to d:f,h packages character- values at -40, +25, +85 apply to e package istic +25 units vo vin vdd (vi (vi (vi -55 -40 +85 +125 min. typ. max. quiescent device - 0,5 5 0.25 0.25 7.5 7.5 - 0.q1 0.25 current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5 100 max. 0,15 15 1 30 - 0.01 p.a - 1 30 1 - 0,20 20 5 5 150 150 - 0.02 5 output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - (sink) current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 26 - iolmin. 1.5 015 15 4.2 4 2.8 2.4 34 6.8 - output high 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - ma (source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -13 -2.6 - ioh min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -;-68 - output voltage: - 0,5 5 0.05 - 0 0.05 low-level, - 0,10 10 0.05 - 0 0.05 vol max. - 0,15 15 005 - 0 0.05 v output voltage: - 0,5 5 4.95 4.95 5 - high-level, - 0,10 10 9.95 9.95 10 - voh min. - 0,15 15 14.95 14.95 15 - input low 0.5,4.5 - 5 1.5 - - 1.5 voltage, 1,9 - 10 3 - - 3 vi~ max. 1.5,13.5 - 15 4 - - 4 3.5 v input high 4.5 - 5 3.5 - - voltage, 9 - 10 7 7 - - vih min. 13.5 - 15 11 11 - - input current 0,18 18 to.l to.l tl tl - t10- 5 0.1 p.a lin max. vod 3 j 4 k f b '0 l e 9 h 12 ii .. g 13 vss cd4071b functional diagram o e f 10 g " h 12 cd4072b functional diagram 9 j 10 l cd4075b functional diagram 238 ______________________________________________________________________ __
cd4071b, cd4072b, cd4075b typ s maximum iratings, absolute-maximum values: dc supply-\'oltage range, (vdd' -0.5 to +20 v (voltages relerenced to vss terminal) input volt~ge range, all inputs dc input current, any one input -0.5 to vdd +0.5 v 10ma power dissipation per package (pol: fcn ta c -40 to +60 o c (package type ei fc)r t a c +60 to +85 0 c (package type ei .. ...... 500mw for t a c -!15 to +100 0 c (package types d,fi for t a c +t 00 to +125 0 c (package types 0, fi derate linearly at 12 mwf'c to 200 mw .. ..... 500mw derate linearly at 12 mw/oc to 200 mw device dissipation per output transistor for t a = full packagetemperature range (all package typesl operatingtemperature range (tal 100mw package types 0, f, h -55 to +125 0 c package type e . -40 to +85 0 c storage te.mperature range (tstgl lead tempe"rature (during solderingi -65 to +150 0 c at d'stance 1/16 1/32 inch (1.59 0 79 mml from case foi 10 s max. dynamic electrical characteristics at t a = 25c, input t r , tf = 20 ns, and cl = 5(] pf, rl =; 200 kn test conditi or ~s all types cha racteristic limits ,- , v ie do typ. ilts propagat ion delay time, 5 125 ':phl' tplh 10 60 45 transltio input ca~ '15 n time, 5 100 tthl' ttlh '10 50 '15 40 ,acitance, cin any input ,- 5 vdd "ss a dd * all inputs are protected by cosimos protection - --- network "ss 92cs29114 fig. 3 - schematic diagram for cd40118 (1of 4 identical gates). 1(6'8'131~r--~ ~ l/~ ~3(4,io,1i1 a 2 (5,9,121 92cii-291l9 fig. 5 - logic diagram for cd40118 (1of 4 identical gates). max. 250 120 90 200 100 80 7.5 units ns ns pf input voltage (v,n' - v fig. 1 - typical voltage transfer characteristics. load capacitance (cli-.f fig. 2 - typical propagation delay time as a function of/oad capacitance. , drain-to-source voltage ivdsi-v fig. 4 - typical output low (sink) current character/stics. drain-to-source voltage lvosl-v fig. 6 - minimum output low (sink) current characteristics. __________________ ---------------------------239
cd4071b, cd4072b, cd4075b typ s inv i vss - - - * all inputs are protecteo ,5 yoo by cos'mos protection network vss fig. 7 - schematic diagram for cd40728 (1 of 2 identical gates). 2 (12) 3 (11) 11131 6 (9) 4 (10) fig. 9 - logic diagram for cd40728 (1 of 2 identical gates). . , .. ,,,:-1 2 (4,'2)0----4- .. 1 (3,11)o*---+---~ vs: ,5-- yoo * all inputs are protecteo by cos 'mos protection network vss ~2c" 2911~ fig. 11 - schematic diagram for cd40758 (1 of 3 identical gates). fig. 13 - logic diagram for cd40758 (1 of 3 identical gates). diiain-ld-source voltage ivos)-v '1'u-l4.j201.) fig. 8 - typical output high (source) current characteristics. drain-lo-source voltage ivdsi-v fig. 10 - minimum output high (source) current charactf!,istics . fig. 12 - typical transition tim.e as a function of loed capacitance. 00": _nt tlill'ellatuii[ it a -25c . - t ~iv vi-' ... i i ,,~ v /1; :- 10". ~ i7l,.?oiy~ ~ - . ~ - ","'~v ~iq! i h // ~ ! iv 1// i 1// iii()2 i i cl~ p' - v cl'15 of --- ii i i --'!l i' i ?? '0-. fig. 14 - typical dyanamic power dissipation ., as a function o( frequency. '0 10' iq! 'nput frequ[ncy (0 1'- .h, 240 ____________________________________________________________________ _
cd4071b, cd4072b, cd4075b typ s terminal assignments (top view) '[ 14 voo j"a+b+c+o i. 14 b- 2 13 h 2 13 j-a+b- 3 12 0 12 k"c+o- 4 ii ""o+h c- :i 10 l"e+f 10 o 6 9 xc 6 9 vss- vss 7 b c04ci7ib cd4072b .2cs-24"'4 xc" internal connection do not use v~.p(ju' ,~ :::;".,,~ o """"'..::.,r- seouentially. vss to both voo and vss connect all unused inputs to either voo crv ss vss 92c5-27402 fig. 16 - input current test circuit. vs.~uto ,~ '~'~ v 1l ? .j note 92cs-z144" i vss ~srn'p~~0m8inati()n fig. 17 - input-voltage test circuit. voo k"e+i'+ii+h h 0 f e xc 92cs-l""96ri d,menslolls .n parentheses are .n mll.',meters and are deflved from the basic .nch d""e.1slons as .n. d,cated gfld graduations are .n mils (10- 3 .nch) the photographs and d,mensions of t~ach cdsimds chip represent a chip when it is part of the wafer when the w~fer is cut into" chip~, the cleavage angles are 57 instead of 90 with respect to the face of the chip therefore, the nola ted chip is actually 7 mils (0 17 mm) larger in both dimensions dimensions and pad layout for cd4072b. voo o l"o+h+x k"o+e+f j "a+b+c vss -"'l..-_.llr-c cd4d7!18 92cs-244'" o vss inputs do vss 9zcs-zr4l0iai fig. 15 - oulescent device current test circuit. '2es-2'1i1 dimensions and pad layout for cd4071 b. .au-hi 10 dimensions and pad layout for cd4075b. ___________________________________________ 241
|
